This nonprovisional application claims priority under 35 U.S.C. xc2xa7119(a) on Patent Application No. 2001-336822 and 2002-303845 filed in JAPAN on Nov. 1, 2001 and Oct. 18, 2002, which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to a transistor, a semiconductor memory including the same, and a method of manufacturing a transistor. More particularly, the present invention relates to a technology useful for a semiconductor memory having storage cells each storing multiple bits.
2. Description of the Background Art
Today, nonvolatile memories including EEPROMs (Electrically Erasable Programmable Read-Only Memories) are widely applied to, e.g. mobile telephones. An EEPROM, for example, usually allows only one bit of information to be stored in each storage cell transistor. However, to promote size reduction of the device, there should preferably be implemented the multiple-bit configuration of a cell transistor that allows two or more bits of information to be stored in the cell transistor.
FIG. 29 of the drawings shows a storage cell transistor with a multiple-bit configuration taught in U.S. Pat. No. 6,011,725 by way of example. As shown, the cell transistor, generally 1, has a so-called MONOS (Metal Oxide Nitride Oxide Semiconductor) structure made up of a control gate electrode (metal) 7, a silicon oxide layer (oxide) 6, a silicon nitride layer (nitride) 5, a silicon oxide layer (oxide) 4, and a P type silicon substrate (semiconductor) 2 in the order.
In the cell transistor 1, N type source/drain regions 3 and 8 each selectively become a source or a drain electrode at various stages of a write-in or a read-out sequence. In other words, it is indefinite which of the source/drain regions 3 and 8 functions as a source or a drain electrode. In the following description, one of the source/drain regions 3 and 8 that discharges an electric carrier, which may be electrons in this specific case, and the other region will be referred to as a source and a drain region, respectively.
FIG. 30A demonstrates how data is written to the storage cell transistor 1. As shown, the source region 8 is grounded while suitable positive voltages VD1 and VG1 are applied to the drain region 3 and the control gate 7, respectively. In this condition, an electric field is established between the source region 8 and the drain region 3 and accelerates electrons, so that hot electrons are generated in the vicinity of the drain region 3. The hot electrons thus generated are injected into the silicon nitride layer 5 over the potential barrier formed by the silicon oxide layer 4 due to the collision thereof against phonons and the positive potential of the control gate electrode 7. Because the silicon nitride layer 5 is not electrically conductive, the hot electrons injected into the silicon nitride layer 5 localize in the vicinity of the drain region 3, forming a right bit 9a of information stored. This storage condition is representative of a stored-bit state (1, 0).
FIG. 30B shows a condition wherein the source and drain voltages of FIG. 30A are replaced with each other. As shown, the hot electrons injected into the silicon nitride layer 5 localize in the vicinity of the drain region 8, forming a left bit 9b of information stored. This sets up a storage state (0, 1).
FIGS. 31A through 31D show four different logical storage states available with the cell transistor 1. As shown in FIG. 31A, when electrons are not stored in either one of the right and left bit positions, a state (1, 1) is set up. As shown in FIG. 31D, when electrons are stored in both of the right and left bit positions, a state (0, 0) is set up. In this manner, the cell transistor 1 allows two-bit data to be stored therein. To read out the data from the cell transistor 1, the voltages applied to the source region 8 and drain region 3 are replaced with each other from write-in condition to measure a drain current two times while each drain current measured is compared with a reference current value, as will be described more specifically hereinafter.
In the state (0, 0) shown in FIG. 31D, electrons localize at both of the right and left bit positions 9a and 9b, so that the potential of the silicon nitride layer 5 is lowest among the four states. Consequently, the threshold voltage of the cell transistor 1 becomes highest and causes substantially no drain current to flow. The value of the drain current remains the same even when the voltages applied to the source region 8 and drain region 3 are replaced, and is almost zero. As a result, the drain currents sequentially measured both are determined to be smaller than the reference current.
In the state (1, 1) shown in FIG. 31A, electrons are absent from both of the right and left bit positions 9a and 9b, so that the potential of the silicon nitride layer 5 is highest among the four states. Therefore, the threshold voltage of the transistor 1 becomes lowest among the four states, causing the greatest drain current to flow. The value of the drain current remains the same even when the source region 8 and drain region 3 are replaced with each other, and is greatest among the four states. As a result, the drain currents measured one after the other are both determined to be greater than the reference current.
On the other hand, in the states (1, 0) and (0, 1) shown in FIGS. 31B and 31C, respectively, electrons localize at only one of the right and left bit positions, making the cell transistor 1 asymmetrical in the right-and-left direction with respect to potential distribution. The drain currents sequentially measured are different from each other when the voltages applied to the source region 8 and drain region 3 are replaced. It is therefore possible to distinguish the states (1, 0) and (0, 1) by determining which of the two drain currents sequentially measured is greater or smaller than the reference current.
However, the cell transistor 1 with the structure described above has some problems left unsolved, as will be described hereinafter. First, in the event of write-in, see FIGS. 30A and 30B, to allow hot electrons to be injected into the silicon nitride layer 5, the high voltage VG1 must be applied to the control gate 7. More specifically, for the injection of hot electrons, it is necessary to tunnel hot electrons from the conduction band of the silicon substrate 2 to the conduction band of the silicon oxide layer 4. An energy difference between the above two conduction bands is about 3.2 electron volts (eV). However, the hot electrons lose energy on colliding against phonons present in the silicon substrate 2 and cannot be tunneled between the two conduction bands mentioned above even if a voltage of 3.2 volts (V) is applied to the control gate 7. In practice, therefore, the voltage VG1 applied to the control gate 7 must be as high as 12 V to 13 V.
While the above high voltage is expected to be applied to the control gate 7 from a highly voltage-resistant transistor included in a decoder circuit, not shown, such a transistor cannot be miniaturized because miniaturization would cause punch-through to occur between the source and the drain electrode of the transistor. It is therefore impossible with the prior art structure described above to reduce the chip size of the entire EEPROM including the decoder circuit.
Second, the current window for distinguishing the drain currents is smaller when the state (1, 0) or (0, 1) is sensed. A current window refers to a difference between the drain currents measured one after the other by replacing the voltages applied to the source and drain regions 3 and 8 in the event of sensing the states (1, 0) and (0, 1) The current window definitely opens when electrons distinctly localize at the right end or the left end of the silicon nitride layer 5, i.e. when the cell transistor 1 is clearly asymmetrical in the right-and-left direction in potential or electron distribution.
Asymmetry, however, does not clearly appear in the cell transistor 1 because electrons are distributed in the silicon nitride layer 5 over some breadth. Particularly, when a gate length L, see FIG. 30A, is reduced for reducing the cell size, it is not clear at which of the right and left bit positions electrons localize, further reducing the asymmetry of the cell transistor 1 and therefore the current window. Such a small current window reduces the margins of the drain and reference currents and thereby aggravates incorrect identification of stored data.
Third, resistance to inter-band tunneling available with the prior art structure is low, as will be described herein after with reference to FIG. 32. FIG. 32 shows a condition wherein the cell transistor 1 is not selected. As shown, to make the cell transistor 1 unselected, a ground potential lower than the potential assigned to read-out is applied to the control gate 7. On the other hand, the positive potential VD1 is applied to the drain electrode of a cell transistor selected. Because the positive potential VD1 is common to all of the cells in the direction of column of the memory device, it is applied to the drain region 3 of the cell transistor 1 as well.
In the condition shown in FIG. 32, a potential difference xcex94V between the silicon nitride layer 5 and the drain region 3 is greater than in the case off read-out because the potential of the control gate 7 is lowered. Particularly, when electrons localize in the silicon nitride layer 5, the potential difference xcex94V further increases because the electrons lower the potential of the silicon nitride layer 5. If the potential difference xcex94V is great, then a tunnel current flows between the drain region 3 and the silicon nitride layer 5 and causes the silicon oxide layer 4 to deteriorate.
Moreover, a greater potential difference xcex94V produces a stronger electric field at the edge of the drain region 3, so that breakdown is apt to occur at the PN junction of the drain region 3 and silicon substrate 2. The breakdown causes hot holes and electrons to appear in pairs, as shown in an enlarged view in a circle 100 in the figure. The hot holes 102 are attracted toward the lower potential side and therefore passed through the silicon oxide layer 4, deteriorating the layer 4. The low resistance to inter-band tunneling mentioned earlier refers to the circumstances described above.
It is an object of the present invention to provide a multiple-bit transistor capable of writing data with a reduced voltage with an increased current window and higher resistance to inter-band tunneling achieved than conventional, a semiconductor memory including such a multiple-bit transistor, and a method of manufacturing such a multiple-bit transistor.
In accordance with the present invention, a transistor comprising a one-conductivity type semiconductor substrate formed with a projection having a pair of side walls facing each other, a first insulation layer formed on a top of the projection, a pair of source/drain regions formed on a surface of the semiconductor substrate at both sides of the projection, second insulation layers each covering one of the pair of side walls and one of said source/drain regions adjoining the side wall, a pair of floating gates respectively formed on the pair of side walls of the projection and respectively facing the side walls and the source/drain regions via respective second insulation layers, third insulation layers each being formed on one of the floating gates, and a control gate facing the pair of floating gates via third insulation layers and facing the top of the projection via the first insulation layer. The projection has a root portion formed to connect the source/drain regions with a straight line, the root portion being higher in concentration of the one conductivity type of impurity than a remaining portion of the projection.
Alternatively, the control gate may form a first capacitance against the top of the projection via the first insulation layer, and the floating gates may form a second capacitance against the side walls of the projection and the source/drain regions via the second insulation layers, the second capacitance being higher than the first capacitance.
Further alternatively, the floating gates may be coupled in capacitance with a second capacitance established against the side walls and of the projection and the source/drain regions via the second insulation layers, and a third capacitance established against the control gate via the third insulation layers, the second capacitance being formed larger.
Alternatively, the transistor may further comprise counter-conductivity type regions formed on the side walls of the projection and contacting the source/drain regions.
Advantageously, the control gate may comprise first control gate segments facing the floating gates via the third insulation layers and a second control gate segment facing the top of the projection via the first insulation layer. The first and second control gates may be formed to be electrically interconnected. Alternatively, the first and second control gates may be formed to be controlled electrically independently of each other.
Also, in accordance with the present invention, a semiconductor memory includes a plurality of cell transistors each having the configuration described above.
Further, in accordance with the present invention, a method of manufacturing a transistor, comprising the steps of implanting an impurity into a primary surface of a one-conductivity type semiconductor substrate to form a first region with lower impurity concentration and a second region with higher impurity concentration in an order from the primary surface in a depth direction of the substrate, forming trenches in the primary surface to a depth at which the trench has a bottom reaching the second region to form a projection having a pair of side walls opposite to each other, implanting a counter-conductivity type impurity in the bottom of the trench to form a source/drain region at the bottom, forming a first insulation layer on the source/drain region and the side walls of the trench, forming a floating gate at least partially on the side walls of the projection and the source/drain region via the first insulation layer, forming a second insulation layer on a top of the projection, forming a third insulation layer on the floating gate, and forming a control gate on the second and third insulation layers.